A phase-locked loop (PLL) is a closed-loop feedback control system that maintains a generated signal in a fixed phase relationship to a reference signal. Since an integrated cicuit (IC) can hold a complete PLL building block, the technique is widely used in modern electronic devices, with signal frequencies from a fraction of a cycle per second up to many gigahertz.
Typically a PLL may include a lock detector that monitors REF (reference) and FB (feedback) edges to signal when the PLL is in lock. This lock signal is often used as a way to judge if there is a short clock cycle (i.e., a fast clock signal) in order to avoid corrupted data in an IC. However, this application of the lock signal may not work properly because the lock detector is not actually monitoring the clock out signal. In addition, the resolution of the lock detector may be considerably larger than the timing closure window.
Conventionally, the short clock cycle is avoided by calculating the statistical probability of the short clock cycle and increasing the timing uncertainty such that the rate of such an occurrence is acceptable to the design of an IC. However, using this approach, the IC will eventually get a bit error. Furthermore, the current calculations are based on silicon measurements that are not available in the early product life.
Thus, it would be desirable to provide a system and method which may effectively address the foregoing-described problems.